1. Field of the Invention
The present invention relates to a multi-layer printed circuit board for use in a computer mother board with human detectable layer misregistration, a camera-incorporated multi-chip module (VTR MCM), a chip size package (CSP), a portable phone and the like, and a manufacturing method therefor. Particularly, the present invention relates to a multi-layer printed circuit board and a manufacturing method therefor, in which a wrong disposing of layers and/or eccentricity can be easily detected.
2. Description of the Prior Art
In the midst of progress of the internal installation of electronic components, the multi-layer printed circuit board was invented. Since that time, studies have been briskly carried out to make the printed circuit board highly dense.
Recently, in accordance with the trend of high speed and high density of the electronic apparatuses, the printed circuit board in a numerously stacked form has been demanded, and therefore, the printed circuit board has become more complicated.
Generally, a multi-layer printed circuit board includes a copper clad laminate (to be called "CCL" below) which is formed by cladding copper foils on the both faces of an insulating layer. The multi-layer printed circuit board further includes inner circuited layers and outer circuited layers, which are stacked on the CCL, and on which circuit patterns are printed.
FIG. 1 illustrates the manufacturing process for the usual multi-layer printed circuit board in which six layers are stacked.
As shown in FIGS. 1A and 1B, in the case of a 6-layer circuit board, in order to form inner circuited layers 10, circuit patterns 14 are formed on the both faces of a CCL 11 by applying a photo-etching method as designed in advance. Then another CCL 13 is formed on which patterns are formed in the same way.
As shown in FIG. 1C, the inner circuited layers 10 can be obtained by disposing a plurality of the inner circuited layers on a CCL art work film 1. The CCL 11 and 13 form the inner circuited layers 10 after going through a stacking process as shown in FIG. 1B.
Specifically, in forming the inner circuited layers 10, an adhesive insulating sheet such as a prepreg 12 is stacked between the CCLs 11 and 13, and then, heat and pressure are applied. Under this condition, if two or more CCLs are used to form 4 or more inner circuited layers, then 6 or more circuited layers can be obtained unlike that illustrated in the drawings.
Then the inner circuited layers 10 are subjected to drillings, and then are electroplated. Then a via hole 15 is formed for electric conductions between the inner circuited layers. Thus, the inner circuited layers are formed.
Then as shown in FIG. 1D, prepregs 22 and 24 are stacked on the uppermost and lowermost faces of the inner circuited layers 10. Then in order to form outer circuited layers, CCLs or thin copper films 21 and 23 are stacked, and then the whole circuit board layers are subjected to heating and pressing.
Then as shown in FIG. 1E, a drilling and an electroplating are carried out on the circuit board as when forming the inner circuited layers, so as to form a through hole 25. The multi-layer printed circuit board thus formed is spread with a resist paste, and finally a routing is carried out by cutting with a router.
However, when manufacturing the above described multi-layer printed circuit board, during the stacking of the inner circuited layers and during the stacking of the inner and outer circuited layers, a circuit incoherence (circuit mismatching) (also to be called "misregistration") may occur depending on the skill of the worker and on a tolerance departure of a stacking pin (not shown in the drawings).
FIG. 2 illustrates an example of the circuit misregistration which has occurred during the stacking process. That is, FIG. 2A illustrates that a via hole 15a for making a second layer and a fifth layer electrically conducted is severely mismatched due to the misregistration during the stacking of the inner circuited layers 10.
FIG. 2B illustrates that the stacking of the inner and outer circuited layers is mismatched, and that a pattern 26a is severely mismatched at the through hole 25 (which is for making the outer circuited layers electrically conducted).
If such a misregistration occurs, the finished products are likely to show a lowered performance. If a less severe misregistration has occurred, electrical signals are emitted even during the final inspection, and therefore, the finished product makes it difficult to discriminate the defect, if a precise inspection is not carried out.
Meanwhile, during the manufacture of the usual multi-layer printed circuit board, a wrong disposing of the layers may occur either due to the short skill of the workers or by a process error. In this case, the problem is more serious than the misregistration. That is, in this case, the electrical characteristic values are considerably lowered. Accordingly, the finished products may show a severely lowered performance or have to be discarded, such cases being quite frequent.
Conventionally, in order to prevent the wrong disposing of layers, a number mark 40 is provided at a part of each layer 30 as shown in FIG. 3A. This number mark 40 shows the sequence of the stacking of the layers. FIG. 3B is a detailed illustration of FIG. 3A, and it shows a second layer.
To describe it based on a specific example, the following arrangements are provided in advance before stacking as shown in FIG. 3C. That is, arabic numerals 41-46 are marked on the both faces of the layers starting from the lowermost layer 37 (the first layer), through the second and third layers of the CCL 33, through the fourth and fifth layers of the CCL 31 and to the uppermost circuited layer 35. Thus the number mark 40 is provided.
The number mark 40 can be formed by photo-etching a copper foil or by attaching arabic numerals. Since prepregs 32, 36 and 38 are disposed between the circuited layers, and since the insulating layers between the CCLs are transparent, recognitions are possible to a certain degree if the number of the stacked layers is not large.
However, in the conventional technique in which the sequence of the layers is indicated by the arabic numerals, as the number of the stacked layers is increased, the arabic numerals indicating the sequence became non-recognizable. Therefore, not only the detection of the wrong disposing has become difficult, but particularly the misregistration cannot be checked. Furthermore, even if a wrong disposing of layers occurs, an electric checker cannot detect the abnormality. In addition, if a misregistration is passed as non-abnormal, then the electrical characteristic values are lowered, with the result that the product quality is greatly aggravated. Particularly in the case of the wrong disposing of layers, if the characteristic values are different after the installation of the component, a disorder may occur.
Therefore, a means for recognizing the misregistration and the wrong disposing of layers is in demand.